1. Field of the Invention
The present invention relates to a method for forming semiconductor devices and, more particularly, to a method for forming Schottky diodes in a CMOS process.
2. Description of the Related Art.
A Schottky diode is a metal-to-semiconductor structure which is physically similar to a metal contact; essentially differing only in that the Schottky diode is formed on a lightly-doped region of the substrate, while the metal contact is formed on a heavily-doped region of the substrate.
Although physically similar, the Schottky diode and the metal contact exhibit very different current-to-voltage (I/V) relationships. This difference is due to the different dopant concentrations that are used in the two substrate regions.
The Schottky diode, which is formed on the lightly-doped region, has a current-to-voltage (I/V) relationship that is similar to the I/V relationship of a pn diode. That is, when forward biased, a Schottky diode provides a low-resistance current path and, when reverse-biased, a high-resistance current path. On the other hand, the metal contact, which is formed on the heavily-doped region, has a I/V relationship that is linear or resistive.
FIG. 1 shows a cross-sectional diagram that illustrates a wafer 100 which has a conventionally formed Schottky diode and a conventionally formed metal contact. As shown in FIG. 1, wafer 100 includes a n-type semiconductor material 110, such as a substrate or a well, and a plurality of field oxide isolation regions FOX which are formed in material 110.
Wafer 100 also includes a n+ region 112 and a p+ region 114 which are both formed in material 110, and a nxe2x88x92 region 116 which is defined in material 110. N+ region 112 represents the heavily-doped substrate region of a biasing contact, while p+ region 114 represents the heavily-doped source and drain regions of a CMOS transistor. Nxe2x88x92 region 116, in turn, represents the lightly-doped substrate region of a Schokkty diode.
As further shown in FIG. 1, wafer 100 also includes a layer of planarized silicon dioxide 120 which is formed over material 110 and the field oxide isolation regions FOX. Layer 120, in turn, has an opening 122 which exposes n+ region 112, an opening 124 which exposes p+ region 114, and an opening 126 which exposes nxe2x88x92 region 116.
Wafer 100 additionally includes a layer of titanium 128 which is formed over regions 112, 114, and 116, and the sidewalls of the openings 122, 124, and 126, and a layer of titanium nitride 130 which is formed over titanium layer 128. Titanium layer 128 and titanium nitride layer 130 form a diffusion barrier to prevent junction spiking. (Part of titanium layer 130 is converted into titanium silicide during the heat treatments that are associated with contact formation.)
Further, wafer 100 Includes an aluminum or tungsten plug 132 which is formed over titanium nitride layer 130 in opening 122, an aluminum or tungsten plug 134 which is formed over titanium nitride layer 130 in opening 124, and an aluminum or tungsten plug 136 which is formed over titanium nitride layer 130 in opening 126. In addition, a plurality of aluminum lines 138, 140, and 142 are connected to plugs 132, 134, and 136, respectively, and other lines to realize the underlying electrical circuit.
As shown in FIG. 1, a substrate biasing contact 144 is formed by n+ region 112, barrier layers 128 and 130, and plug 132, while a source/drain contact 146 is formed by p+ region 114, barrier layers 128 and 130, and plug 134. Further, a Schottky diode 148 is formed by n-region 116, barrier layers 128 and 130 (titanium/titanium silicide and titanium nitride), and plug 136.
One of the problems with Schottky diode 148, however, is that the minimum size of diode 148 is typically determined by the minimum contact size that is available in the photolithographic process. As a result, diode 148 consumes a significant amount of silicon real estate (substrate surface area). Thus, there is a need for a Schottky diode that requires less silicon real estate.
Conventionally, Schottky diodes require a significant amount of silicon real estate as the minimum size of the diode is typically limited to the minimum contact size that is available. The present invention eliminates the silicon real estate required by the diode by forming the Schottky diode through a field oxide isolation region.
In accordance with the present invention, a wafer, which has a Schottky diode, includes a semiconductor material which has a first conductivity type and a first dopant concentration, and a first region which is formed in the semiconductor material. The first region has a second conductivity type and a second dopant concentration.
The wafer also includes a field oxide isolation region which is formed in the semiconductor material, the field oxide isolation region has a first opening that extends through the field oxide isolation region.
The wafer further includes a second region which is defined in the semiconductor material to adjoin the first opening in the field oxide isolation region, and a layer of insulation material which is formed over the first region and the field oxide isolation region. The second region has the first conductivity type and the first dopant concentration.
The layer of insulation material has a second opening that extends through the layer of insulation material, and a third opening that extends through the layer of insulation material. The second opening adjoins the first region while the third opening adjoins the first opening.
The wafer additionally includes a layer of barrier material which is formed on the sidewalls of the second opening, the first region, the sidewalls of the first and third openings, and the second region. Further, a first metal plug is formed in the second opening to contact the layer of barrier material, while a second metal plug is formed in the first and third openings to contact the layer of barrier material.
The present invention also includes a method for forming a Schottky diode in a wafer. The wafer has a semiconductor material which has a first conductivity type and a first dopant concentration, and a first region that is formed in the semiconductor material. The first region has a second conductivity type and a second dopant concentration.
The wafer also has a field oxide region that is formed in the semiconductor material, a second region which is defined in the semiconductor material below the field oxide region, and a layer of insulation material which is formed over the first region and the field oxide region.
The method of the present invention comprises the steps of selectively removing the layer of insulation material to form a first opening that exposes the first region to form an exposed first region, and a second opening that exposes the second region to form an exposed second region.
The method also includes the steps of forming a layer of barrier material on the layer of insulation material, the exposed first region, and the exposed second region, and forming a layer of metal over the layer of barrier material.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.